ECS643U/ECS720P – Power Electronics

Coursework 4: MATLAB/Simulink Experiment for DC-DC Converters

Deadline for Report Submission: 01/12/2025

Important Notes:

• Submit your answers within the specified deadline. Late submissions will not be accepted.
• Reference all sources used (textbooks, notes, online materials) according to normal academic standards. Plagiarism or copying from other students/resources will result in a mark of 0 with no video viva.
• Multiple submissions are not permitted. Check your submission carefully before uploading.
• The use of calculators and MATLAB (any version) is allowed.

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Report Submission

• Upload one PDF document to the QM+ portal under “Assessment Submission”.
• Include all Simulink/Simscape models and MATLAB codes in your report.
• Students are expected to simulate multiple separate models in one coursework.

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Marking

• This coursework contributes 25% of the final module mark.
• Final marks will be published on the QM+ page.

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Coursework Objectives

1. Model an open-loop synchronous buck converter.
2. Model a closed-loop synchronous buck converter with an analog controller.
3. Investigate load transient response and perform simulations.

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Question 1 – Open-Loop Buck DC-DC Converter

Setup:

• Circuit components:
  • ( R = 4.1 , Omega )
  • ( L = 80 , mu H )
  • ( C = 5 , mu F )
  • Ground connection
• Input DC voltage: ( V_{in} = 100 , V )
• Current measurement: ( 0.42 , A )
• Voltage measurement: ( 12 , V )
• Scope: ( 1 , Omega )

Instructions:

1. Open MATLAB → Simulink.
2. Open preconfigured model: buck_open_loop.mdl.
3. Adjust simulation parameters:
   • Stop time: 10 ms
   • Max step size: 0.1 μs (1/100 of switching period)

Tasks:

1a. Include scope output waveforms for ( V_o ) and ( I_L ).
1b. Change duty cycle (D) and fill Table 1:

Experiment	Duty Cycle (D)	( V_o ) (Steady-State)	( V_o / V_{in} )
1	0.2
2	0.3
3	0.5
4	0.7
5	0.9

1c. Explain why the ( V_o / V_{in} ) ratio differs from the ideal duty cycle ratio (use formulas and circuit analysis).
1d. Complete the state-space diagram based on the three main differential equations of a buck converter.

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Question 2 – Closed-Loop Buck Converter Control

Objective: Construct and simulate a closed-loop voltage regulator using a continuous-time integral compensator.

Setup:

• Use PWM and Buck converter blocks from Question 1.
• Compensator parameters:
  • Gain1 = 0.4 (voltage divider)
  • Gain2 = 1000 (integral compensator)
  • Constant = 2 V (Vref, so steady-state ( V_o = 5 , V ))

Tasks:

2a. Include output waveforms ( V_o ) and ( I_L ).

2b. Vary Gain2 values and record rise time, overshoot, and waveforms in Table 2:

Experiment	Gain2	( V_o ) Waveform	Rise Time (s)	Overshoot (%)
1	800
2	2000
3	3000

2c. Specify system response type: overdamped, underdamped, or critically damped.
2d. Discuss:

• Which response reaches steady state earliest?
• Which response has higher overshoot?
• Relationship between system agility and overshoot.
• Advantages/disadvantages of each response type.

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Question 3 – Step Response of Buck DC-DC Converter

Objective: Investigate load transient behavior under closed-loop control.

Setup:

• Step load pulse generator: Step total load from 1 Ω → 2 Ω and back.
• Parameters:
  • Amplitude = 1
  • Period = 2 ms
  • Pulse width = 50%

Tasks:

3a. Change Gain2 values (Table 3) and report ( V_o ) waveform, settling time, and overshoot:

Experiment	Gain2	( V_o ) Waveform	Settling Time (s)	Overshoot (%)
1	800
2	2000
3	3000

3b. Compare step responses across the three Gain2 settings:

• Settling time
• Rise time
• Overshoot

3c. Determine which compensator topology meets the DC load requirement:

• Settling time < 0.3 ms for 1 Ω load transient
• Compare rise time and overshoot for your selected topology

Submission Notes

• Include all simulation screenshots, waveforms, MATLAB/Simulink models, and calculations in the PDF report.
• Follow academic integrity rules.

This structured version is now concise, readable, and suitable for students to follow easily.