ECS643U / ECS720P – Power Electronics

Coursework Examination 4

MATLAB/Simulink Experiment for DC–DC Converters

Deadline: 01/12/2025
Weight: 25% of total module mark

Instructions

• You must submit your answers before the deadline from the moment the coursework is released.
• You may refer to textbooks, lecture notes, and online resources, but:
  • You must cite all sources used.
  • Normal plagiarism rules apply.
  • Any detected plagiarism or copying (from students or external sources) will result in a mark of 0 with no viva offered.
• Multiple submissions are not allowed. Check your file before uploading.
• Use of calculators and MATLAB (any version) is permitted.
• Submit a single PDF document containing:
  • All answers
  • All requested discussions
  • All MATLAB scripts and Simulink/Simscape models (screenshots/code)
• Upload via QM+ → Assessment Submission.
• Final marks will be published on QM+.

Coursework Objectives

You will build and analyse:

1. Open-loop synchronous buck converter model
2. Closed-loop synchronous buck converter with analogue controller
3. Load transient simulation and analysis

Question 1 – Open-loop Buck DC–DC Converter

A preconfigured Simulink model (buck_open_loop.mdl) represents the Buck Converter subsystem.

Required circuit components:

• R=4.1ΩR = 4.1 OmegaR=4.1Ω
• L=80 mHL = 80 , text{mH}L=80mH
• C=376 μFC = 376 , mu FC=376μF
• Load =5Ω= 5 Omega=5Ω
• Input DC voltage: VS=100 VV_S = 100,VVS​=100V
• Duty cycle initial value: D=0.42D = 0.42D=0.42
• Measurements: inductor current iLi_LiL​, output voltage VoV_oVo​
• Ground, Scope

Simulation Setup

• Set Stop Time = 10 ms
• Set Max step size ≈ 1/100 × switching period (e.g., 0.1 μs)

Question 1a

Include the scope output waveforms for:

• Output voltage VoV_oVo​
• Inductor current ILI_LIL​

Question 1b

Change the duty cycle (D) and complete Table 1 with steady-state values.

Table 1 – Duty Cycle vs Output

Question 1c

Explain why Vo/VinV_o / V_{in}Vo​/Vin​ is not equal to the expected duty cycle (D).

Include:

• Formula-based explanation
• Circuit-level analysis
• Real-world effects (e.g., losses, parasitics, diode drops, switching behaviour)

Question 1d

Using the three main differential equations of the buck converter:

diLdt=…,dvodt=…,State-space form based on iL,vofrac{di_L}{dt} = dots , quad frac{dv_o}{dt} = dots , quad text{State-space form based on } i_L, v_odtdiL​​=…,dtdvo​​=…,State-space form based on iL​,vo​

Complete the given block diagram for the converter.

Hints:

• State variables are iLi_LiL​ and vov_ovo​.
• There are separate equations for switch ON and OFF states.

Question 2 – Closed-loop Control of Buck Converter

You will construct a closed-loop regulator using a continuous-time integral compensator.
Use the PWM and Buck Converter blocks from Question 1.

Compensator Parameters

• Gain1 (voltage divider sensing gain HHH) = 0.4
• Gain2 (integral gain) = 1000
• Constant (reference voltage VrefV_{ref}Vref​) = 2 V

Thus steady-state goal:

Vo=VrefH=5VV_o = frac{V_{ref}}{H} = 5VVo​=HVref​​=5V

Question 2a

Include output waveforms for:

• VoV_oVo​
• ILI_LIL​

Question 2b

Change Gain2 according to Table 2.
Include waveforms and complete required values:

Table 2 – Closed-loop Performance

Definitions provided:

• Rise Time → Time to reach 90% of steady-state
• Overshoot → Peak % over steady-state
• Settling Time → Time to reach ±2% band

Question 2c

Determine response type for each experiment:

• Overdamped
• Underdamped
• Critically damped

Question 2d – Discussion

Discuss:

• Which response reaches steady state earliest (not rise time)?
• Which response has the highest overshoot?
• Relationship between system agility and overshoot
• Advantages and disadvantages of:
  • Overdamped
  • Underdamped
  • Critically damped

Question 3 – Step Response of Buck Converter

You will simulate load transients using a Step Load Pulse Generator.

Step Load Block Settings

• Amplitude: 1
• Period: 2 ms
• Pulse Width: 50%

This steps the total load resistance:

• 0–1 ms → 2Ω2Omega2Ω
• 1–2 ms → 1Ω1Omega1Ω
• 2–3 ms → 2Ω2Omega2Ω
• … and repeats

Step changes are instantaneous.

Question 3a

Change Gain2 values as in Table 3 and include:

• Output waveform
• Settling time
• Overshoot

Table 3 – Step Response Test

Question 3b

Compare step responses in terms of:

1. Settling time
2. Rise time
3. Overshoot

Discuss differences across all three experiments.

Question 3c

The converter must supply a DC load where:

• Settling time < 0.3 ms for a 1Ω load transient

Determine which compensator configuration (Gain2 value from Q3a):

• Meets the settling time requirement
• Performs best when balancing rise time and overshoot

Provide justification